Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

Authors

  • Shourin Rahman Aura Lecturer, Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology, Dhaka, Bangladesh
  • S. M. Ishraqul Huq Assistant Professor, Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology, Dhaka, Bangladesh
  • Satyendra N. Biswas Professor, Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology, Dhaka, Bangladesh

DOI:

https://doi.org/10.32985/ijeces.13.9.11

Keywords:

SRAM, CMOS, dual port, figure of merit

Abstract

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

Downloads

Published

2022-12-06

How to Cite

[1]
Shourin Rahman Aura, S. M. Ishraqul Huq, and Satyendra N. Biswas, “Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature”, IJECES, vol. 13, no. 9, pp. 823-829, Dec. 2022.

Issue

Vol. 13 No. 9 (2022)

Section

Original Scientific Papers