Area and Power Optimized Architecture of Sample Rate Converter for IoT Gateway Applications

Abstract

Nowadays, the Internet of things plays a major role in society for various applications such as medical diagnostics, telecommunications, agriculture, mobile computing, broadcasting, video surveillance etc. In Internet of Things (IoT) networks, several sensors with different data rates should be integrated to perform overall control or monitoring processes.High-speed data transmission technologies should be needed to communicate with IoT servers or storage. Generally, a gateway device is used to integrate low-data rate devices and IoT interfaces. Field Programmable Gate Array Logic (FPGA) can be utilized to implement high-speed and low-power gateway. The paper suggests a design of an FPGA-based IoT gateway architecture, which allows multi-protocol communications and an effective way of controlling sample rates. The design provides RF transceivers, protocol specific modules, and dynamic Sample Rate (SR) Selector to support smooth synchronization of data between diverse IoT devices. Clock generation and control blocks guarantee adaptive frequency assignment and upsampling and downsampling CIC filtering-based units ensure good signal conditioning. Experimental analysis shows that the presented method creates the low root mean square error (RMSE): 1.2 percent (downlink) and 1.4 percent (uplink), and high signal to noise ratios (SNR): 26.3 dB (downlink) and 24.8 dB (uplink) in 45 nm CMOS technology, resulting in better results than conventional 180 nm implementations. The Application-Specific Integrated Circuit (ASIC) implementation achieved a compact core area, reducing from 2.3 μm2 at 180 nm to 0.3 μm2 at 45 nm, demonstrating significant area efficiency with technology scaling. The results affirm that the architecture can provide reliable and high-quality data transfers of next-generation IoT gateways.